238 lines
5.9 KiB
ArmAsm
238 lines
5.9 KiB
ArmAsm
/*
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* Copyright © 2022 Rémi Denis-Courmont.
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*
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* This file is part of FFmpeg.
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*
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* FFmpeg is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* FFmpeg is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with FFmpeg; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "asm.S"
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// (a0) = (a1) * (a2) [0..a3-1]
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func ff_vector_fmul_rvv, zve32f
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1:
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vsetvli t0, a3, e32, m1, ta, ma
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vle32.v v16, (a1)
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sub a3, a3, t0
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vle32.v v24, (a2)
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sh2add a1, t0, a1
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vfmul.vv v16, v16, v24
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sh2add a2, t0, a2
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vse32.v v16, (a0)
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sh2add a0, t0, a0
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bnez a3, 1b
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ret
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endfunc
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// (a0) += (a1) * fa0 [0..a2-1]
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func ff_vector_fmac_scalar_rvv, zve32f
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NOHWF fmv.w.x fa0, a2
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NOHWF mv a2, a3
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1:
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vsetvli t0, a2, e32, m1, ta, ma
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slli t1, t0, 2
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vle32.v v24, (a1)
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sub a2, a2, t0
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vle32.v v16, (a0)
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sh2add a1, t0, a1
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vfmacc.vf v16, fa0, v24
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vse32.v v16, (a0)
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sh2add a0, t0, a0
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bnez a2, 1b
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ret
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endfunc
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// (a0) = (a1) * fa0 [0..a2-1]
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func ff_vector_fmul_scalar_rvv, zve32f
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NOHWF fmv.w.x fa0, a2
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NOHWF mv a2, a3
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1:
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vsetvli t0, a2, e32, m1, ta, ma
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vle32.v v16, (a1)
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sub a2, a2, t0
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vfmul.vf v16, v16, fa0
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sh2add a1, t0, a1
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vse32.v v16, (a0)
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sh2add a0, t0, a0
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bnez a2, 1b
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ret
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endfunc
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func ff_vector_fmul_window_rvv, zve32f
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// a0: dst, a1: src0, a2: src1, a3: window, a4: length
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addi t0, a4, -1
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add t1, t0, a4
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sh2add a2, t0, a2
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sh2add t0, t1, a0
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sh2add t3, t1, a3
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li t1, -4 // byte stride
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1:
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vsetvli t2, a4, e32, m1, ta, ma
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vle32.v v16, (a1)
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slli t4, t2, 2
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vlse32.v v20, (a2), t1
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sub a4, a4, t2
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vle32.v v24, (a3)
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add a1, a1, t4
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vlse32.v v28, (t3), t1
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sub a2, a2, t4
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vfmul.vv v0, v16, v28
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add a3, a3, t4
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vfmul.vv v8, v16, v24
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sub t3, t3, t4
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vfnmsac.vv v0, v20, v24
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vfmacc.vv v8, v20, v28
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vse32.v v0, (a0)
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add a0, a0, t4
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vsse32.v v8, (t0), t1
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sub t0, t0, t4
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bnez a4, 1b
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ret
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endfunc
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// (a0) = (a1) * (a2) + (a3) [0..a4-1]
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func ff_vector_fmul_add_rvv, zve32f
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1:
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vsetvli t0, a4, e32, m1, ta, ma
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vle32.v v8, (a1)
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sub a4, a4, t0
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vle32.v v16, (a2)
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sh2add a1, t0, a1
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vle32.v v24, (a3)
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sh2add a2, t0, a2
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vfmadd.vv v8, v16, v24
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sh2add a3, t0, a3
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vse32.v v8, (a0)
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sh2add a0, t0, a0
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bnez a4, 1b
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ret
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endfunc
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// (a0) = (a1) * reverse(a2) [0..a3-1]
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func ff_vector_fmul_reverse_rvv, zve32f
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sh2add a2, a3, a2
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li t2, -4 // byte stride
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addi a2, a2, -4
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1:
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vsetvli t0, a3, e32, m1, ta, ma
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slli t1, t0, 2
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vle32.v v16, (a1)
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sub a3, a3, t0
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vlse32.v v24, (a2), t2
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add a1, a1, t1
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vfmul.vv v16, v16, v24
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sub a2, a2, t1
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vse32.v v16, (a0)
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add a0, a0, t1
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bnez a3, 1b
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ret
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endfunc
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// (a0) = (a0) + (a1), (a1) = (a0) - (a1) [0..a2-1]
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func ff_butterflies_float_rvv, zve32f
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1:
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vsetvli t0, a2, e32, m1, ta, ma
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vle32.v v16, (a0)
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sub a2, a2, t0
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vle32.v v24, (a1)
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vfadd.vv v0, v16, v24
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vfsub.vv v8, v16, v24
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vse32.v v0, (a0)
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sh2add a0, t0, a0
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vse32.v v8, (a1)
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sh2add a1, t0, a1
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bnez a2, 1b
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ret
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endfunc
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// a0 = (a0).(a1) [0..a2-1]
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func ff_scalarproduct_float_rvv, zve32f
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vsetvli zero, zero, e32, m1, ta, ma
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vmv.s.x v8, zero
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1:
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vsetvli t0, a2, e32, m1, ta, ma
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vle32.v v16, (a0)
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sub a2, a2, t0
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vle32.v v24, (a1)
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sh2add a0, t0, a0
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vfmul.vv v16, v16, v24
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sh2add a1, t0, a1
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vfredusum.vs v8, v16, v8
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bnez a2, 1b
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vfmv.f.s fa0, v8
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NOHWF fmv.x.w a0, fa0
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ret
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endfunc
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// (a0) = (a1) * (a2) [0..a3-1]
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func ff_vector_dmul_rvv, zve64d
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1:
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vsetvli t0, a3, e64, m1, ta, ma
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vle64.v v16, (a1)
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sub a3, a3, t0
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vle64.v v24, (a2)
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sh3add a1, t0, a1
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vfmul.vv v16, v16, v24
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sh3add a2, t0, a2
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vse64.v v16, (a0)
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sh3add a0, t0, a0
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bnez a3, 1b
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ret
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endfunc
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// (a0) += (a1) * fa0 [0..a2-1]
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func ff_vector_dmac_scalar_rvv, zve64d
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NOHWD fmv.d.x fa0, a2
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NOHWD mv a2, a3
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1:
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vsetvli t0, a2, e64, m1, ta, ma
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vle64.v v24, (a1)
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sub a2, a2, t0
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vle64.v v16, (a0)
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sh3add a1, t0, a1
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vfmacc.vf v16, fa0, v24
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vse64.v v16, (a0)
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sh3add a0, t0, a0
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bnez a2, 1b
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ret
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endfunc
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// (a0) = (a1) * fa0 [0..a2-1]
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func ff_vector_dmul_scalar_rvv, zve64d
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NOHWD fmv.d.x fa0, a2
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NOHWD mv a2, a3
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1:
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vsetvli t0, a2, e64, m1, ta, ma
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vle64.v v16, (a1)
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sub a2, a2, t0
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vfmul.vf v16, v16, fa0
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sh3add a1, t0, a1
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vse64.v v16, (a0)
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sh3add a0, t0, a0
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bnez a2, 1b
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ret
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endfunc
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