Rémi Denis-Courmont 4fe8f2cc43 riscv: allow passing addend to vtype_vli macro ...

A constant (-1) is added to the length value, so we can have an added
for free, and optimise the addition away if the addend is exactly 1.

2024-05-30 18:30:52 +03:00

..

asm.S

riscv: allow passing addend to vtype_vli macro

2024-05-30 18:30:52 +03:00

bswap_rvb.S

riscv: factor out the bswap32 assembler

2023-10-02 22:28:21 +03:00

bswap.h

…

cpu.c

lavu/riscv: fix parsing the unaligned access capability

2024-05-15 20:04:08 +03:00

cpu.h

lavu/riscv: add ff_rv_vlen_least()

2024-05-13 18:36:07 +03:00

fixed_dsp_init.c

lavu/fixed_dsp: R-V V fmul_window_scaled

2023-11-23 18:57:18 +02:00

fixed_dsp_rvv.S

lavu/fixed_dsp: R-V V fmul_window_scaled

2023-11-23 18:57:18 +02:00

float_dsp_init.c

…

float_dsp_rvv.S

lavu/float_dsp: optimise R-V V fmul_reverse & fmul_window

2023-11-23 18:57:18 +02:00

intmath.h

…

Makefile

…

timer.h

Revert "lavu/timer: remove gratuitous volatile"

2023-09-28 17:48:18 +03:00