419145c11b
The 8x4 and 4x4 use a needlessly large multiplier (unless/until we care about embedded 64-bit-vector hardware). This is merely suboptimal. The 8x4 case also uses an incorrect vector length, which leads to incorrect behaviour on future/hypothetical hardware with 256-bit or larger vectors. Pointed-out-by: Martin Storsjö <martin@martin.st>
114 lines
3.8 KiB
ArmAsm
114 lines
3.8 KiB
ArmAsm
/*
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* Copyright (c) 2023 Institue of Software Chinese Academy of Sciences (ISCAS).
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*
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* This file is part of FFmpeg.
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*
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* FFmpeg is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* FFmpeg is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with FFmpeg; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "libavutil/riscv/asm.S"
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func ff_vc1_inv_trans_8x8_dc_rvv, zve64x
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lh t2, (a2)
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vsetivli zero, 8, e8, mf2, ta, ma
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vlse64.v v0, (a0), a1
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sh1add t2, t2, t2
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addi t2, t2, 1
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srai t2, t2, 1
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sh1add t2, t2, t2
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addi t2, t2, 16
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srai t2, t2, 5
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li t0, 8*8
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vsetvli zero, t0, e16, m8, ta, ma
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vzext.vf2 v8, v0
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vadd.vx v8, v8, t2
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vmax.vx v8, v8, zero
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vsetvli zero, zero, e8, m4, ta, ma
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vnclipu.wi v0, v8, 0
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vsetivli zero, 8, e8, mf2, ta, ma
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vsse64.v v0, (a0), a1
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ret
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endfunc
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func ff_vc1_inv_trans_4x8_dc_rvv, zve32x
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lh t2, (a2)
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vsetivli zero, 8, e8, mf2, ta, ma
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vlse32.v v0, (a0), a1
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slli t1, t2, 4
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add t2, t2, t1
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addi t2, t2, 4
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srai t2, t2, 3
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sh1add t2, t2, t2
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slli t2, t2, 2
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addi t2, t2, 64
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srai t2, t2, 7
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li t0, 4*8
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vsetvli zero, t0, e16, m4, ta, ma
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vzext.vf2 v4, v0
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vadd.vx v4, v4, t2
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vmax.vx v4, v4, zero
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vsetvli zero, zero, e8, m2, ta, ma
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vnclipu.wi v0, v4, 0
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vsetivli zero, 8, e8, mf2, ta, ma
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vsse32.v v0, (a0), a1
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ret
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endfunc
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func ff_vc1_inv_trans_8x4_dc_rvv, zve64x
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lh t2, (a2)
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vsetivli zero, 4, e8, mf4, ta, ma
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vlse64.v v0, (a0), a1
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sh1add t2, t2, t2
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addi t2, t2, 1
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srai t2, t2, 1
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slli t1, t2, 4
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add t2, t2, t1
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addi t2, t2, 64
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srai t2, t2, 7
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li t0, 8*4
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vsetvli zero, t0, e16, m4, ta, ma
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vzext.vf2 v4, v0
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vadd.vx v4, v4, t2
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vmax.vx v4, v4, zero
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vsetvli zero, zero, e8, m2, ta, ma
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vnclipu.wi v0, v4, 0
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vsetivli zero, 4, e8, mf4, ta, ma
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vsse64.v v0, (a0), a1
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ret
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endfunc
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func ff_vc1_inv_trans_4x4_dc_rvv, zve32x
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lh t2, (a2)
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vsetivli zero, 4, e8, mf4, ta, ma
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vlse32.v v0, (a0), a1
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slli t1, t2, 4
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add t2, t2, t1
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addi t2, t2, 4
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srai t2, t2, 3
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slli t1, t2, 4
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add t2, t2, t1
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addi t2, t2, 64
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srai t2, t2, 7
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vsetivli zero, 4*4, e16, m2, ta, ma
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vzext.vf2 v2, v0
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vadd.vx v2, v2, t2
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vmax.vx v2, v2, zero
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vsetvli zero, zero, e8, m1, ta, ma
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vnclipu.wi v0, v2, 0
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vsetivli zero, 4, e8, mf4, ta, ma
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vsse32.v v0, (a0), a1
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ret
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endfunc
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