365 lines
18 KiB
C
365 lines
18 KiB
C
/*
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* Loongson SIMD utils
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*
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* Copyright (c) 2016 Loongson Technology Corporation Limited
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* Copyright (c) 2016 Zhou Xiaoyong <zhouxiaoyong@loongson.cn>
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*
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* This file is part of FFmpeg.
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*
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* FFmpeg is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* FFmpeg is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with FFmpeg; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef AVUTIL_MIPS_MMIUTILS_H
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#define AVUTIL_MIPS_MMIUTILS_H
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#include "config.h"
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#include "libavutil/mips/asmdefs.h"
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#if HAVE_LOONGSON2
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#define DECLARE_VAR_LOW32 int32_t low32
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#define RESTRICT_ASM_LOW32 [low32]"=&r"(low32),
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#define DECLARE_VAR_ALL64 int64_t all64
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#define RESTRICT_ASM_ALL64 [all64]"=&r"(all64),
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#define DECLARE_VAR_ADDRT mips_reg addrt
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#define RESTRICT_ASM_ADDRT [addrt]"=&r"(addrt),
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#define MMI_LWX(reg, addr, stride, bias) \
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PTR_ADDU "%[addrt], "#addr", "#stride" \n\t" \
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"lw "#reg", "#bias"(%[addrt]) \n\t"
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#define MMI_SWX(reg, addr, stride, bias) \
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PTR_ADDU "%[addrt], "#addr", "#stride" \n\t" \
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"sw "#reg", "#bias"(%[addrt]) \n\t"
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#define MMI_LDX(reg, addr, stride, bias) \
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PTR_ADDU "%[addrt], "#addr", "#stride" \n\t" \
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"ld "#reg", "#bias"(%[addrt]) \n\t"
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#define MMI_SDX(reg, addr, stride, bias) \
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PTR_ADDU "%[addrt], "#addr", "#stride" \n\t" \
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"sd "#reg", "#bias"(%[addrt]) \n\t"
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#define MMI_LWC1(fp, addr, bias) \
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"lwc1 "#fp", "#bias"("#addr") \n\t"
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#define MMI_ULWC1(fp, addr, bias) \
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"ulw %[low32], "#bias"("#addr") \n\t" \
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"mtc1 %[low32], "#fp" \n\t"
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#define MMI_LWXC1(fp, addr, stride, bias) \
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PTR_ADDU "%[addrt], "#addr", "#stride" \n\t" \
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MMI_LWC1(fp, %[addrt], bias)
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#define MMI_SWC1(fp, addr, bias) \
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"swc1 "#fp", "#bias"("#addr") \n\t"
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#define MMI_USWC1(fp, addr, bias) \
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"mfc1 %[low32], "#fp" \n\t" \
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"usw %[low32], "#bias"("#addr") \n\t"
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#define MMI_SWXC1(fp, addr, stride, bias) \
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PTR_ADDU "%[addrt], "#addr", "#stride" \n\t" \
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MMI_SWC1(fp, %[addrt], bias)
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#define MMI_LDC1(fp, addr, bias) \
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"ldc1 "#fp", "#bias"("#addr") \n\t"
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#define MMI_ULDC1(fp, addr, bias) \
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"uld %[all64], "#bias"("#addr") \n\t" \
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"dmtc1 %[all64], "#fp" \n\t"
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#define MMI_LDXC1(fp, addr, stride, bias) \
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PTR_ADDU "%[addrt], "#addr", "#stride" \n\t" \
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MMI_LDC1(fp, %[addrt], bias)
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#define MMI_SDC1(fp, addr, bias) \
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"sdc1 "#fp", "#bias"("#addr") \n\t"
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#define MMI_USDC1(fp, addr, bias) \
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"dmfc1 %[all64], "#fp" \n\t" \
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"usd %[all64], "#bias"("#addr") \n\t"
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#define MMI_SDXC1(fp, addr, stride, bias) \
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PTR_ADDU "%[addrt], "#addr", "#stride" \n\t" \
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MMI_SDC1(fp, %[addrt], bias)
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#define MMI_LQ(reg1, reg2, addr, bias) \
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"ld "#reg1", "#bias"("#addr") \n\t" \
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"ld "#reg2", 8+"#bias"("#addr") \n\t"
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#define MMI_SQ(reg1, reg2, addr, bias) \
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"sd "#reg1", "#bias"("#addr") \n\t" \
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"sd "#reg2", 8+"#bias"("#addr") \n\t"
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#define MMI_LQC1(fp1, fp2, addr, bias) \
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"ldc1 "#fp1", "#bias"("#addr") \n\t" \
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"ldc1 "#fp2", 8+"#bias"("#addr") \n\t"
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#define MMI_SQC1(fp1, fp2, addr, bias) \
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"sdc1 "#fp1", "#bias"("#addr") \n\t" \
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"sdc1 "#fp2", 8+"#bias"("#addr") \n\t"
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#elif HAVE_LOONGSON3 /* !HAVE_LOONGSON2 */
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#define DECLARE_VAR_ALL64
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#define RESTRICT_ASM_ALL64
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#define DECLARE_VAR_ADDRT
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#define RESTRICT_ASM_ADDRT
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#define MMI_LWX(reg, addr, stride, bias) \
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"gslwx "#reg", "#bias"("#addr", "#stride") \n\t"
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#define MMI_SWX(reg, addr, stride, bias) \
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"gsswx "#reg", "#bias"("#addr", "#stride") \n\t"
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#define MMI_LDX(reg, addr, stride, bias) \
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"gsldx "#reg", "#bias"("#addr", "#stride") \n\t"
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#define MMI_SDX(reg, addr, stride, bias) \
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"gssdx "#reg", "#bias"("#addr", "#stride") \n\t"
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#define MMI_LWC1(fp, addr, bias) \
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"lwc1 "#fp", "#bias"("#addr") \n\t"
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#if _MIPS_SIM == _ABIO32 /* workaround for 3A2000 gslwlc1 bug */
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#define DECLARE_VAR_LOW32 int32_t low32
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#define RESTRICT_ASM_LOW32 [low32]"=&r"(low32),
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#define MMI_ULWC1(fp, addr, bias) \
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"ulw %[low32], "#bias"("#addr") \n\t" \
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"mtc1 %[low32], "#fp" \n\t"
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#else /* _MIPS_SIM != _ABIO32 */
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#define DECLARE_VAR_LOW32
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#define RESTRICT_ASM_LOW32
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#define MMI_ULWC1(fp, addr, bias) \
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"gslwlc1 "#fp", 3+"#bias"("#addr") \n\t" \
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"gslwrc1 "#fp", "#bias"("#addr") \n\t"
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#endif /* _MIPS_SIM != _ABIO32 */
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#define MMI_LWXC1(fp, addr, stride, bias) \
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"gslwxc1 "#fp", "#bias"("#addr", "#stride") \n\t"
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#define MMI_SWC1(fp, addr, bias) \
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"swc1 "#fp", "#bias"("#addr") \n\t"
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#define MMI_USWC1(fp, addr, bias) \
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"gsswlc1 "#fp", 3+"#bias"("#addr") \n\t" \
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"gsswrc1 "#fp", "#bias"("#addr") \n\t"
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#define MMI_SWXC1(fp, addr, stride, bias) \
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"gsswxc1 "#fp", "#bias"("#addr", "#stride") \n\t"
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#define MMI_LDC1(fp, addr, bias) \
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"ldc1 "#fp", "#bias"("#addr") \n\t"
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#define MMI_ULDC1(fp, addr, bias) \
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"gsldlc1 "#fp", 7+"#bias"("#addr") \n\t" \
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"gsldrc1 "#fp", "#bias"("#addr") \n\t"
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#define MMI_LDXC1(fp, addr, stride, bias) \
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"gsldxc1 "#fp", "#bias"("#addr", "#stride") \n\t"
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#define MMI_SDC1(fp, addr, bias) \
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"sdc1 "#fp", "#bias"("#addr") \n\t"
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#define MMI_USDC1(fp, addr, bias) \
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"gssdlc1 "#fp", 7+"#bias"("#addr") \n\t" \
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"gssdrc1 "#fp", "#bias"("#addr") \n\t"
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#define MMI_SDXC1(fp, addr, stride, bias) \
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"gssdxc1 "#fp", "#bias"("#addr", "#stride") \n\t"
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#define MMI_LQ(reg1, reg2, addr, bias) \
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"gslq "#reg1", "#reg2", "#bias"("#addr") \n\t"
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#define MMI_SQ(reg1, reg2, addr, bias) \
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"gssq "#reg1", "#reg2", "#bias"("#addr") \n\t"
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#define MMI_LQC1(fp1, fp2, addr, bias) \
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"gslqc1 "#fp1", "#fp2", "#bias"("#addr") \n\t"
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#define MMI_SQC1(fp1, fp2, addr, bias) \
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"gssqc1 "#fp1", "#fp2", "#bias"("#addr") \n\t"
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#endif /* HAVE_LOONGSON2 */
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/**
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* backup register
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*/
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#define BACKUP_REG \
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LOCAL_ALIGNED_16(double, temp_backup_reg, [8]); \
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if (_MIPS_SIM == _ABI64) \
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__asm__ volatile ( \
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"gssqc1 $f25, $f24, 0x00(%[temp]) \n\t" \
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"gssqc1 $f27, $f26, 0x10(%[temp]) \n\t" \
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"gssqc1 $f29, $f28, 0x20(%[temp]) \n\t" \
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"gssqc1 $f31, $f30, 0x30(%[temp]) \n\t" \
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: \
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: [temp]"r"(temp_backup_reg) \
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: "memory" \
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); \
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else \
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__asm__ volatile ( \
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"gssqc1 $f22, $f20, 0x00(%[temp]) \n\t" \
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"gssqc1 $f26, $f24, 0x10(%[temp]) \n\t" \
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"gssqc1 $f30, $f28, 0x20(%[temp]) \n\t" \
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: \
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: [temp]"r"(temp_backup_reg) \
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: "memory" \
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);
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/**
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* recover register
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*/
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#define RECOVER_REG \
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if (_MIPS_SIM == _ABI64) \
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__asm__ volatile ( \
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"gslqc1 $f25, $f24, 0x00(%[temp]) \n\t" \
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"gslqc1 $f27, $f26, 0x10(%[temp]) \n\t" \
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"gslqc1 $f29, $f28, 0x20(%[temp]) \n\t" \
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"gslqc1 $f31, $f30, 0x30(%[temp]) \n\t" \
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: \
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: [temp]"r"(temp_backup_reg) \
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: "memory" \
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); \
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else \
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__asm__ volatile ( \
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"gslqc1 $f22, $f20, 0x00(%[temp]) \n\t" \
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"gslqc1 $f26, $f24, 0x10(%[temp]) \n\t" \
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"gslqc1 $f30, $f28, 0x20(%[temp]) \n\t" \
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: \
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: [temp]"r"(temp_backup_reg) \
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: "memory" \
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);
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/**
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* brief: Transpose 2X2 word packaged data.
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* fr_i0, fr_i1: src
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* fr_o0, fr_o1: dst
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*/
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#define TRANSPOSE_2W(fr_i0, fr_i1, fr_o0, fr_o1) \
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"punpcklwd "#fr_o0", "#fr_i0", "#fr_i1" \n\t" \
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"punpckhwd "#fr_o1", "#fr_i0", "#fr_i1" \n\t"
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/**
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* brief: Transpose 4X4 half word packaged data.
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* fr_i0, fr_i1, fr_i2, fr_i3: src & dst
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* fr_t0, fr_t1, fr_t2, fr_t3: temporary register
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*/
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#define TRANSPOSE_4H(fr_i0, fr_i1, fr_i2, fr_i3, \
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fr_t0, fr_t1, fr_t2, fr_t3) \
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"punpcklhw "#fr_t0", "#fr_i0", "#fr_i1" \n\t" \
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"punpckhhw "#fr_t1", "#fr_i0", "#fr_i1" \n\t" \
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"punpcklhw "#fr_t2", "#fr_i2", "#fr_i3" \n\t" \
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"punpckhhw "#fr_t3", "#fr_i2", "#fr_i3" \n\t" \
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"punpcklwd "#fr_i0", "#fr_t0", "#fr_t2" \n\t" \
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"punpckhwd "#fr_i1", "#fr_t0", "#fr_t2" \n\t" \
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"punpcklwd "#fr_i2", "#fr_t1", "#fr_t3" \n\t" \
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"punpckhwd "#fr_i3", "#fr_t1", "#fr_t3" \n\t"
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/**
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* brief: Transpose 8x8 byte packaged data.
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* fr_i0~i7: src & dst
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* fr_t0~t3: temporary register
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*/
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#define TRANSPOSE_8B(fr_i0, fr_i1, fr_i2, fr_i3, fr_i4, fr_i5, \
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fr_i6, fr_i7, fr_t0, fr_t1, fr_t2, fr_t3) \
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"punpcklbh "#fr_t0", "#fr_i0", "#fr_i1" \n\t" \
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"punpckhbh "#fr_t1", "#fr_i0", "#fr_i1" \n\t" \
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"punpcklbh "#fr_t2", "#fr_i2", "#fr_i3" \n\t" \
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"punpckhbh "#fr_t3", "#fr_i2", "#fr_i3" \n\t" \
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"punpcklbh "#fr_i0", "#fr_i4", "#fr_i5" \n\t" \
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"punpckhbh "#fr_i1", "#fr_i4", "#fr_i5" \n\t" \
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"punpcklbh "#fr_i2", "#fr_i6", "#fr_i7" \n\t" \
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"punpckhbh "#fr_i3", "#fr_i6", "#fr_i7" \n\t" \
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"punpcklhw "#fr_i4", "#fr_t0", "#fr_t2" \n\t" \
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"punpckhhw "#fr_i5", "#fr_t0", "#fr_t2" \n\t" \
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"punpcklhw "#fr_i6", "#fr_t1", "#fr_t3" \n\t" \
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"punpckhhw "#fr_i7", "#fr_t1", "#fr_t3" \n\t" \
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"punpcklhw "#fr_t0", "#fr_i0", "#fr_i2" \n\t" \
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"punpckhhw "#fr_t1", "#fr_i0", "#fr_i2" \n\t" \
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"punpcklhw "#fr_t2", "#fr_i1", "#fr_i3" \n\t" \
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"punpckhhw "#fr_t3", "#fr_i1", "#fr_i3" \n\t" \
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"punpcklwd "#fr_i0", "#fr_i4", "#fr_t0" \n\t" \
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"punpckhwd "#fr_i1", "#fr_i4", "#fr_t0" \n\t" \
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"punpcklwd "#fr_i2", "#fr_i5", "#fr_t1" \n\t" \
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"punpckhwd "#fr_i3", "#fr_i5", "#fr_t1" \n\t" \
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"punpcklwd "#fr_i4", "#fr_i6", "#fr_t2" \n\t" \
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"punpckhwd "#fr_i5", "#fr_i6", "#fr_t2" \n\t" \
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"punpcklwd "#fr_i6", "#fr_i7", "#fr_t3" \n\t" \
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"punpckhwd "#fr_i7", "#fr_i7", "#fr_t3" \n\t"
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/**
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* brief: Parallel SRA for 8 byte packaged data.
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* fr_i0: src
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* fr_i1: SRA number(SRAB number + 8)
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* fr_t0, fr_t1: temporary register
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* fr_d0: dst
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*/
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#define PSRAB_MMI(fr_i0, fr_i1, fr_t0, fr_t1, fr_d0) \
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"punpcklbh "#fr_t0", "#fr_t0", "#fr_i0" \n\t" \
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"punpckhbh "#fr_t1", "#fr_t1", "#fr_i0" \n\t" \
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"psrah "#fr_t0", "#fr_t0", "#fr_i1" \n\t" \
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"psrah "#fr_t1", "#fr_t1", "#fr_i1" \n\t" \
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"packsshb "#fr_d0", "#fr_t0", "#fr_t1" \n\t"
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/**
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* brief: Parallel SRL for 8 byte packaged data.
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* fr_i0: src
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* fr_i1: SRL number(SRLB number + 8)
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* fr_t0, fr_t1: temporary register
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* fr_d0: dst
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*/
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#define PSRLB_MMI(fr_i0, fr_i1, fr_t0, fr_t1, fr_d0) \
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"punpcklbh "#fr_t0", "#fr_t0", "#fr_i0" \n\t" \
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"punpckhbh "#fr_t1", "#fr_t1", "#fr_i0" \n\t" \
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"psrlh "#fr_t0", "#fr_t0", "#fr_i1" \n\t" \
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"psrlh "#fr_t1", "#fr_t1", "#fr_i1" \n\t" \
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"packsshb "#fr_d0", "#fr_t0", "#fr_t1" \n\t"
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#define PSRAH_4_MMI(fp1, fp2, fp3, fp4, shift) \
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"psrah "#fp1", "#fp1", "#shift" \n\t" \
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"psrah "#fp2", "#fp2", "#shift" \n\t" \
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"psrah "#fp3", "#fp3", "#shift" \n\t" \
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"psrah "#fp4", "#fp4", "#shift" \n\t"
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#define PSRAH_8_MMI(fp1, fp2, fp3, fp4, fp5, fp6, fp7, fp8, shift) \
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PSRAH_4_MMI(fp1, fp2, fp3, fp4, shift) \
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PSRAH_4_MMI(fp5, fp6, fp7, fp8, shift)
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/**
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* brief: (((value) + (1 << ((n) - 1))) >> (n))
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* fr_i0: src & dst
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* fr_i1: Operand number
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* fr_t0, fr_t1: temporary FPR
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* gr_t0: temporary GPR
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*/
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#define ROUND_POWER_OF_TWO_MMI(fr_i0, fr_i1, fr_t0, fr_t1, gr_t0) \
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"li "#gr_t0", 0x01 \n\t" \
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"dmtc1 "#gr_t0", "#fr_t0" \n\t" \
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"punpcklwd "#fr_t0", "#fr_t0", "#fr_t0" \n\t" \
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"psubw "#fr_t1", "#fr_i1", "#fr_t0" \n\t" \
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"psllw "#fr_t1", "#fr_t0", "#fr_t1" \n\t" \
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"paddw "#fr_i0", "#fr_i0", "#fr_t1" \n\t" \
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"psraw "#fr_i0", "#fr_i0", "#fr_i1" \n\t"
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#endif /* AVUTILS_MIPS_MMIUTILS_H */
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