c62cb1112f
* commit 'fef906c77c09940a2fdad155b2adc05080e17eda': Move vorbis_inverse_coupling from dsputil to vorbisdspcontext. Conflicts: libavcodec/dsputil.c libavcodec/x86/dsputil_mmx.c Merged-by: Michael Niedermayer <michaelni@gmx.at>
84 lines
3.0 KiB
ArmAsm
84 lines
3.0 KiB
ArmAsm
/*
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* ARM NEON optimised DSP functions
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* Copyright (c) 2008 Mans Rullgard <mans@mansr.com>
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*
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* This file is part of FFmpeg.
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*
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* FFmpeg is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* FFmpeg is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with FFmpeg; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "libavutil/arm/asm.S"
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function ff_vorbis_inverse_coupling_neon, export=1
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vmov.i32 q10, #1<<31
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subs r2, r2, #4
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mov r3, r0
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mov r12, r1
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beq 3f
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vld1.32 {d24-d25},[r1,:128]!
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vld1.32 {d22-d23},[r0,:128]!
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vcle.s32 q8, q12, #0
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vand q9, q11, q10
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veor q12, q12, q9
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vand q2, q12, q8
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vbic q3, q12, q8
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vadd.f32 q12, q11, q2
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vsub.f32 q11, q11, q3
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1: vld1.32 {d2-d3}, [r1,:128]!
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vld1.32 {d0-d1}, [r0,:128]!
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vcle.s32 q8, q1, #0
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vand q9, q0, q10
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veor q1, q1, q9
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vst1.32 {d24-d25},[r3, :128]!
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vst1.32 {d22-d23},[r12,:128]!
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vand q2, q1, q8
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vbic q3, q1, q8
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vadd.f32 q1, q0, q2
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vsub.f32 q0, q0, q3
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subs r2, r2, #8
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ble 2f
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vld1.32 {d24-d25},[r1,:128]!
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vld1.32 {d22-d23},[r0,:128]!
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vcle.s32 q8, q12, #0
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vand q9, q11, q10
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veor q12, q12, q9
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vst1.32 {d2-d3}, [r3, :128]!
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vst1.32 {d0-d1}, [r12,:128]!
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vand q2, q12, q8
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vbic q3, q12, q8
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vadd.f32 q12, q11, q2
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vsub.f32 q11, q11, q3
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b 1b
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2: vst1.32 {d2-d3}, [r3, :128]!
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vst1.32 {d0-d1}, [r12,:128]!
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it lt
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bxlt lr
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3: vld1.32 {d2-d3}, [r1,:128]
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vld1.32 {d0-d1}, [r0,:128]
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vcle.s32 q8, q1, #0
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vand q9, q0, q10
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veor q1, q1, q9
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vand q2, q1, q8
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vbic q3, q1, q8
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vadd.f32 q1, q0, q2
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vsub.f32 q0, q0, q3
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vst1.32 {d2-d3}, [r0,:128]!
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vst1.32 {d0-d1}, [r1,:128]!
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bx lr
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endfunc
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