ARM: NEON optimised MDCT
Originally committed as revision 19819 to svn://svn.ffmpeg.org/ffmpeg/trunk
This commit is contained in:
Måns Rullgård
parent
46c32e2654
commit
edc0f5dcba
@ -164,3 +164,163 @@ function ff_imdct_calc_neon, export=1
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pop {r4-r6,pc}
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pop {r4-r6,pc}
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.endfunc
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.endfunc
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function ff_mdct_calc_neon, export=1
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push {r4-r10,lr}
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mov r12, #1
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ldr lr, [r0, #4] @ nbits
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ldr r4, [r0, #8] @ tcos
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ldr r5, [r0, #12] @ tsin
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ldr r3, [r0, #24] @ revtab
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lsl lr, r12, lr @ n = 1 << nbits
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add r7, r2, lr @ in4u
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sub r9, r7, #16 @ in4d
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add r2, r7, lr, lsl #1 @ in3u
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add r8, r9, lr, lsl #1 @ in3d
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mov r12, #-16
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vld2.32 {d16,d18},[r9,:128],r12 @ x,x in4d1,in4d0
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vld2.32 {d17,d19},[r8,:128],r12 @ x,x in3d1,in3d0
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vld2.32 {d20,d21},[r7,:128]! @ in4u0,in4u1 x,x
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vrev64.32 q9, q9 @ in4d0,in4d1 in3d0,in3d1
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vld2.32 {d0, d1}, [r2,:128]! @ in3u0,in3u1 x,x
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vsub.f32 d20, d18, d20 @ in4d-in4u I
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vld1.32 {d2}, [r4,:64]! @ c0,c1
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vadd.f32 d0, d0, d19 @ in3u+in3d -R
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vld1.32 {d3}, [r5,:64]! @ s0,s1
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1:
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vmul.f32 d7, d20, d3 @ I*s
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vmul.f32 d6, d0, d2 @ -R*c
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ldr r6, [r3], #4
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vmul.f32 d4, d0, d3 @ -R*s
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vmul.f32 d5, d20, d2 @ I*c
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subs lr, lr, #16
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vsub.f32 d6, d6, d7 @ -R*c-I*s
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vadd.f32 d7, d4, d5 @ -R*s+I*c
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uxtah r10, r1, r6, ror #16
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uxtah r6, r1, r6
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beq 1f
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vld2.32 {d16,d18},[r9,:128],r12 @ x,x in4d1,in4d0
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vld2.32 {d17,d19},[r8,:128],r12 @ x,x in3d1,in3d0
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vneg.f32 d7, d7 @ R*s-I*c
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vld2.32 {d20,d21},[r7,:128]! @ in4u0,in4u1 x,x
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vrev64.32 q9, q9 @ in4d0,in4d1 in3d0,in3d1
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vld2.32 {d0, d1}, [r2,:128]! @ in3u0,in3u1 x,x
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vsub.f32 d20, d18, d20 @ in4d-in4u I
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vld1.32 {d2}, [r4,:64]! @ c0,c1
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vadd.f32 d0, d0, d19 @ in3u+in3d -R
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vld1.32 {d3}, [r5,:64]! @ s0,s1
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vst2.32 {d6[0],d7[0]}, [r6,:64]
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vst2.32 {d6[1],d7[1]}, [r10,:64]
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b 1b
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1:
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vneg.f32 d7, d7 @ R*s-I*c
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vst2.32 {d6[0],d7[0]}, [r6,:64]
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vst2.32 {d6[1],d7[1]}, [r10,:64]
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mov r12, #1
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ldr lr, [r0, #4] @ nbits
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lsl lr, r12, lr @ n = 1 << nbits
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sub r8, r2, #16 @ in1d
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add r2, r9, #16 @ in0u
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sub r9, r7, #16 @ in2d
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mov r12, #-16
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vld2.32 {d16,d18},[r9,:128],r12 @ x,x in2d1,in2d0
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vld2.32 {d17,d19},[r8,:128],r12 @ x,x in1d1,in1d0
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vld2.32 {d20,d21},[r7,:128]! @ in2u0,in2u1 x,x
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vrev64.32 q9, q9 @ in2d0,in2d1 in1d0,in1d1
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vld2.32 {d0, d1}, [r2,:128]! @ in0u0,in0u1 x,x
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vsub.f32 d0, d0, d18 @ in0u-in2d R
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vld1.32 {d2}, [r4,:64]! @ c0,c1
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vadd.f32 d20, d20, d19 @ in2u+in1d -I
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vld1.32 {d3}, [r5,:64]! @ s0,s1
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1:
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vmul.f32 d6, d0, d2 @ R*c
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vmul.f32 d7, d20, d3 @ -I*s
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ldr r6, [r3], #4
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vmul.f32 d4, d0, d3 @ R*s
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vmul.f32 d5, d20, d2 @ I*c
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subs lr, lr, #16
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vsub.f32 d6, d7, d6 @ I*s-R*c
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vadd.f32 d7, d4, d5 @ R*s-I*c
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uxtah r10, r1, r6, ror #16
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uxtah r6, r1, r6
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beq 1f
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vld2.32 {d16,d18},[r9,:128],r12 @ x,x in2d1,in2d0
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vld2.32 {d17,d19},[r8,:128],r12 @ x,x in1d1,in1d0
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vld2.32 {d20,d21},[r7,:128]! @ in2u0,in2u1 x,x
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vrev64.32 q9, q9 @ in2d0,in2d1 in1d0,in1d1
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vld2.32 {d0, d1}, [r2,:128]! @ in0u0,in0u1 x,x
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vsub.f32 d0, d0, d18 @ in0u-in2d R
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vld1.32 {d2}, [r4,:64]! @ c0,c1
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vadd.f32 d20, d20, d19 @ in2u+in1d -I
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vld1.32 {d3}, [r5,:64]! @ s0,s1
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vst2.32 {d6[0],d7[0]}, [r6,:64]
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vst2.32 {d6[1],d7[1]}, [r10,:64]
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b 1b
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1:
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vst2.32 {d6[0],d7[0]}, [r6,:64]
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vst2.32 {d6[1],d7[1]}, [r10,:64]
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mov r4, r0
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mov r6, r1
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add r0, r0, #16
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bl ff_fft_calc_neon
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mov r12, #1
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ldr lr, [r4, #4] @ nbits
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ldr r5, [r4, #12] @ tsin
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ldr r4, [r4, #8] @ tcos
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lsl r12, r12, lr @ n = 1 << nbits
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lsr lr, r12, #3 @ n8 = n >> 3
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add r4, r4, lr, lsl #2
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add r5, r5, lr, lsl #2
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add r6, r6, lr, lsl #3
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sub r1, r4, #8
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sub r2, r5, #8
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sub r3, r6, #16
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mov r7, #-16
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mov r12, #-8
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mov r8, r6
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mov r0, r3
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vld2.32 {d0-d1}, [r3,:128], r7 @ d0 =r1,i1 d1 =r0,i0
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vld2.32 {d20-d21},[r6,:128]! @ d20=r2,i2 d21=r3,i3
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vld1.32 {d18}, [r2,:64], r12 @ d18=s1,s0
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1:
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subs lr, lr, #2
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vmul.f32 d7, d0, d18 @ r1*s1,r0*s0
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vld1.32 {d19}, [r5,:64]! @ s2,s3
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vmul.f32 d4, d1, d18 @ i1*s1,i0*s0
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vld1.32 {d16}, [r1,:64], r12 @ c1,c0
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vmul.f32 d5, d21, d19 @ i2*s2,i3*s3
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vld1.32 {d17}, [r4,:64]! @ c2,c3
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vmul.f32 d6, d20, d19 @ r2*s2,r3*s3
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vmul.f32 d24, d0, d16 @ r1*c1,r0*c0
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vmul.f32 d25, d20, d17 @ r2*c2,r3*c3
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vmul.f32 d22, d21, d17 @ i2*c2,i3*c3
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vmul.f32 d23, d1, d16 @ i1*c1,i0*c0
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vadd.f32 d4, d4, d24 @ i1*s1+r1*c1,i0*s0+r0*c0
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vadd.f32 d5, d5, d25 @ i2*s2+r2*c2,i3*s3+r3*c3
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vsub.f32 d6, d22, d6 @ i2*c2-r2*s2,i3*c3-r3*s3
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vsub.f32 d7, d23, d7 @ i1*c1-r1*s1,i0*c0-r0*s0
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vneg.f32 q2, q2
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beq 1f
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vld2.32 {d0-d1}, [r3,:128], r7
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vld2.32 {d20-d21},[r6,:128]!
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vld1.32 {d18}, [r2,:64], r12
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vrev64.32 q3, q3
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vst2.32 {d4,d6}, [r0,:128], r7
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vst2.32 {d5,d7}, [r8,:128]!
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b 1b
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1:
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vrev64.32 q3, q3
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vst2.32 {d4,d6}, [r0,:128]
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vst2.32 {d5,d7}, [r8,:128]
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pop {r4-r10,pc}
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.endfunc
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@ -780,6 +780,7 @@ void ff_imdct_calc_sse(MDCTContext *s, FFTSample *output, const FFTSample *input
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void ff_imdct_half_sse(MDCTContext *s, FFTSample *output, const FFTSample *input);
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void ff_imdct_half_sse(MDCTContext *s, FFTSample *output, const FFTSample *input);
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void ff_imdct_calc_neon(MDCTContext *s, FFTSample *output, const FFTSample *input);
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void ff_imdct_calc_neon(MDCTContext *s, FFTSample *output, const FFTSample *input);
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void ff_imdct_half_neon(MDCTContext *s, FFTSample *output, const FFTSample *input);
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void ff_imdct_half_neon(MDCTContext *s, FFTSample *output, const FFTSample *input);
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void ff_mdct_calc_neon(MDCTContext *s, FFTSample *output, const FFTSample *input);
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void ff_mdct_end(MDCTContext *s);
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void ff_mdct_end(MDCTContext *s);
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/* Real Discrete Fourier Transform */
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/* Real Discrete Fourier Transform */
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@ -119,6 +119,7 @@ av_cold int ff_fft_init(FFTContext *s, int nbits, int inverse)
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s->fft_calc = ff_fft_calc_neon;
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s->fft_calc = ff_fft_calc_neon;
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s->imdct_calc = ff_imdct_calc_neon;
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s->imdct_calc = ff_imdct_calc_neon;
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s->imdct_half = ff_imdct_half_neon;
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s->imdct_half = ff_imdct_half_neon;
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s->mdct_calc = ff_mdct_calc_neon;
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revtab_shift = 3;
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revtab_shift = 3;
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#endif
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#endif
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