Revert "Move H264/QPEL specific asm from dsputil.asm to h264_qpel_*.asm."
This reverts commit f90ff772e7e35b4923c2de429d1fab9f2569b568. The code should be put back in h264_qpel_8bit.asm, but unfortunately it is unconditionally used from dsputil_mmx.c since 71155d7.
This commit is contained in:
Diego Biurrun
parent
399663be9d
commit
e8c52271c4
@ -649,3 +649,194 @@ BSWAP32_BUF
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INIT_XMM ssse3
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BSWAP32_BUF
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; FIXME: All of the code below should be put back in h264_qpel_8bit.asm.
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; Unfortunately it is unconditionally used from dsputil_mmx.c since 71155d7 ..
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%macro op_avgh 3
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movh %3, %2
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pavgb %1, %3
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movh %2, %1
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%endmacro
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%macro op_avg 2
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pavgb %1, %2
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mova %2, %1
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%endmacro
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%macro op_puth 2-3
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movh %2, %1
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%endmacro
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%macro op_put 2
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mova %2, %1
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%endmacro
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; void pixels4_l2_mmxext(uint8_t *dst, uint8_t *src1, uint8_t *src2, int dstStride, int src1Stride, int h)
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%macro PIXELS4_L2 1
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%define OP op_%1h
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cglobal %1_pixels4_l2, 6,6
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movsxdifnidn r3, r3d
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movsxdifnidn r4, r4d
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test r5d, 1
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je .loop
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movd m0, [r1]
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movd m1, [r2]
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add r1, r4
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add r2, 4
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pavgb m0, m1
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OP m0, [r0], m3
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add r0, r3
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dec r5d
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.loop:
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mova m0, [r1]
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mova m1, [r1+r4]
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lea r1, [r1+2*r4]
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pavgb m0, [r2]
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pavgb m1, [r2+4]
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OP m0, [r0], m3
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OP m1, [r0+r3], m3
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lea r0, [r0+2*r3]
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mova m0, [r1]
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mova m1, [r1+r4]
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lea r1, [r1+2*r4]
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pavgb m0, [r2+8]
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pavgb m1, [r2+12]
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OP m0, [r0], m3
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OP m1, [r0+r3], m3
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lea r0, [r0+2*r3]
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add r2, 16
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sub r5d, 4
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jne .loop
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REP_RET
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%endmacro
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INIT_MMX mmxext
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PIXELS4_L2 put
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PIXELS4_L2 avg
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; void pixels8_l2_mmxext(uint8_t *dst, uint8_t *src1, uint8_t *src2, int dstStride, int src1Stride, int h)
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%macro PIXELS8_L2 1
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%define OP op_%1
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cglobal %1_pixels8_l2, 6,6
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movsxdifnidn r3, r3d
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movsxdifnidn r4, r4d
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test r5d, 1
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je .loop
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mova m0, [r1]
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mova m1, [r2]
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add r1, r4
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add r2, 8
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pavgb m0, m1
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OP m0, [r0]
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add r0, r3
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dec r5d
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.loop:
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mova m0, [r1]
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mova m1, [r1+r4]
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lea r1, [r1+2*r4]
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pavgb m0, [r2]
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pavgb m1, [r2+8]
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OP m0, [r0]
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OP m1, [r0+r3]
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lea r0, [r0+2*r3]
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mova m0, [r1]
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mova m1, [r1+r4]
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lea r1, [r1+2*r4]
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pavgb m0, [r2+16]
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pavgb m1, [r2+24]
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OP m0, [r0]
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OP m1, [r0+r3]
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lea r0, [r0+2*r3]
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add r2, 32
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sub r5d, 4
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jne .loop
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REP_RET
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%endmacro
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INIT_MMX mmxext
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PIXELS8_L2 put
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PIXELS8_L2 avg
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; void pixels16_l2_mmxext(uint8_t *dst, uint8_t *src1, uint8_t *src2, int dstStride, int src1Stride, int h)
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%macro PIXELS16_L2 1
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%define OP op_%1
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cglobal %1_pixels16_l2, 6,6
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movsxdifnidn r3, r3d
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movsxdifnidn r4, r4d
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test r5d, 1
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je .loop
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mova m0, [r1]
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mova m1, [r1+8]
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pavgb m0, [r2]
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pavgb m1, [r2+8]
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add r1, r4
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add r2, 16
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OP m0, [r0]
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OP m1, [r0+8]
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add r0, r3
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dec r5d
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.loop:
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mova m0, [r1]
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mova m1, [r1+8]
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add r1, r4
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pavgb m0, [r2]
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pavgb m1, [r2+8]
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OP m0, [r0]
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OP m1, [r0+8]
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add r0, r3
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mova m0, [r1]
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mova m1, [r1+8]
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add r1, r4
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pavgb m0, [r2+16]
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pavgb m1, [r2+24]
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OP m0, [r0]
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OP m1, [r0+8]
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add r0, r3
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add r2, 32
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sub r5d, 2
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jne .loop
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REP_RET
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%endmacro
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INIT_MMX mmxext
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PIXELS16_L2 put
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PIXELS16_L2 avg
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INIT_MMX mmxext
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; void pixels(uint8_t *block, const uint8_t *pixels, int line_size, int h)
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%macro PIXELS48 2
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%if %2 == 4
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%define OP movh
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%else
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%define OP mova
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%endif
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cglobal %1_pixels%2, 4,5
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movsxdifnidn r2, r2d
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lea r4, [r2*3]
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.loop:
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OP m0, [r1]
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OP m1, [r1+r2]
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OP m2, [r1+r2*2]
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OP m3, [r1+r4]
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lea r1, [r1+r2*4]
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%ifidn %1, avg
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pavgb m0, [r0]
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pavgb m1, [r0+r2]
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pavgb m2, [r0+r2*2]
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pavgb m3, [r0+r4]
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%endif
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OP [r0], m0
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OP [r0+r2], m1
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OP [r0+r2*2], m2
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OP [r0+r4], m3
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sub r3d, 4
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lea r0, [r0+r2*4]
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jne .loop
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RET
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%endmacro
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PIXELS48 put, 4
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PIXELS48 avg, 4
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PIXELS48 put, 8
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PIXELS48 avg, 8
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@ -860,172 +860,3 @@ INIT_XMM ssse3
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QPEL16_H_LOWPASS_L2_OP put
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QPEL16_H_LOWPASS_L2_OP avg
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%endif
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; void pixels4_l2_mmxext(uint8_t *dst, uint8_t *src1, uint8_t *src2, int dstStride, int src1Stride, int h)
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%macro PIXELS4_L2 1
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%define OP op_%1h
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cglobal %1_pixels4_l2, 6,6
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movsxdifnidn r3, r3d
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movsxdifnidn r4, r4d
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test r5d, 1
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je .loop
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movd m0, [r1]
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movd m1, [r2]
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add r1, r4
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add r2, 4
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pavgb m0, m1
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OP m0, [r0], m3
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add r0, r3
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dec r5d
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.loop:
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mova m0, [r1]
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mova m1, [r1+r4]
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lea r1, [r1+2*r4]
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pavgb m0, [r2]
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pavgb m1, [r2+4]
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OP m0, [r0], m3
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OP m1, [r0+r3], m3
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lea r0, [r0+2*r3]
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mova m0, [r1]
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mova m1, [r1+r4]
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lea r1, [r1+2*r4]
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pavgb m0, [r2+8]
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pavgb m1, [r2+12]
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OP m0, [r0], m3
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OP m1, [r0+r3], m3
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lea r0, [r0+2*r3]
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add r2, 16
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sub r5d, 4
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jne .loop
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REP_RET
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%endmacro
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INIT_MMX mmxext
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PIXELS4_L2 put
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PIXELS4_L2 avg
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; void pixels8_l2_mmxext(uint8_t *dst, uint8_t *src1, uint8_t *src2, int dstStride, int src1Stride, int h)
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%macro PIXELS8_L2 1
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%define OP op_%1
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cglobal %1_pixels8_l2, 6,6
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movsxdifnidn r3, r3d
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movsxdifnidn r4, r4d
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test r5d, 1
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je .loop
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mova m0, [r1]
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mova m1, [r2]
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add r1, r4
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add r2, 8
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pavgb m0, m1
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OP m0, [r0]
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add r0, r3
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dec r5d
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.loop:
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mova m0, [r1]
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mova m1, [r1+r4]
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lea r1, [r1+2*r4]
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pavgb m0, [r2]
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pavgb m1, [r2+8]
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OP m0, [r0]
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OP m1, [r0+r3]
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lea r0, [r0+2*r3]
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mova m0, [r1]
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mova m1, [r1+r4]
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lea r1, [r1+2*r4]
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pavgb m0, [r2+16]
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pavgb m1, [r2+24]
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OP m0, [r0]
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OP m1, [r0+r3]
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lea r0, [r0+2*r3]
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add r2, 32
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sub r5d, 4
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jne .loop
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REP_RET
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%endmacro
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INIT_MMX mmxext
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PIXELS8_L2 put
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PIXELS8_L2 avg
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; void pixels16_l2_mmxext(uint8_t *dst, uint8_t *src1, uint8_t *src2, int dstStride, int src1Stride, int h)
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%macro PIXELS16_L2 1
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%define OP op_%1
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cglobal %1_pixels16_l2, 6,6
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movsxdifnidn r3, r3d
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movsxdifnidn r4, r4d
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test r5d, 1
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je .loop
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mova m0, [r1]
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mova m1, [r1+8]
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pavgb m0, [r2]
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pavgb m1, [r2+8]
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add r1, r4
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add r2, 16
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OP m0, [r0]
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OP m1, [r0+8]
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add r0, r3
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dec r5d
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.loop:
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mova m0, [r1]
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mova m1, [r1+8]
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add r1, r4
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pavgb m0, [r2]
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pavgb m1, [r2+8]
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OP m0, [r0]
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OP m1, [r0+8]
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add r0, r3
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mova m0, [r1]
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mova m1, [r1+8]
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add r1, r4
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pavgb m0, [r2+16]
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pavgb m1, [r2+24]
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OP m0, [r0]
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OP m1, [r0+8]
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add r0, r3
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add r2, 32
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sub r5d, 2
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jne .loop
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REP_RET
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%endmacro
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INIT_MMX mmxext
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PIXELS16_L2 put
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PIXELS16_L2 avg
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INIT_MMX mmxext
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; void pixels(uint8_t *block, const uint8_t *pixels, int line_size, int h)
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%macro PIXELS48 2
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%if %2 == 4
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%define OP movh
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%else
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%define OP mova
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%endif
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cglobal %1_pixels%2, 4,5
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movsxdifnidn r2, r2d
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lea r4, [r2*3]
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.loop:
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OP m0, [r1]
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OP m1, [r1+r2]
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OP m2, [r1+r2*2]
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OP m3, [r1+r4]
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lea r1, [r1+r2*4]
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%ifidn %1, avg
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pavgb m0, [r0]
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pavgb m1, [r0+r2]
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pavgb m2, [r0+r2*2]
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pavgb m3, [r0+r4]
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%endif
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OP [r0], m0
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OP [r0+r2], m1
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OP [r0+r2*2], m2
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OP [r0+r4], m3
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sub r3d, 4
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lea r0, [r0+r2*4]
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jne .loop
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RET
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%endmacro
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PIXELS48 put, 4
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PIXELS48 avg, 4
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PIXELS48 put, 8
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PIXELS48 avg, 8
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