x86/tx_float: add permute-free FFT versions
These are used in the PFA transforms and MDCTs.
This commit is contained in:
Lynne
parent
350142560b
commit
28bff6ae54
@ -707,13 +707,21 @@ cglobal fft4_ %+ %1 %+ _float, 4, 4, 3, ctx, out, in, stride
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FFT4 fwd, 0
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FFT4 inv, 1
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%macro FFT8_FN 2
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INIT_XMM sse3
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cglobal fft8_float, 4, 4, 6, ctx, out, in, tmp
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cglobal fft8_ %+ %1, 4, 4, 6, ctx, out, in, tmp
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%if %2
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mov ctxq, [ctxq + AVTXContext.map]
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LOAD64_LUT m0, inq, ctxq, (mmsize/2)*0, tmpq
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LOAD64_LUT m1, inq, ctxq, (mmsize/2)*1, tmpq
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LOAD64_LUT m2, inq, ctxq, (mmsize/2)*2, tmpq
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LOAD64_LUT m3, inq, ctxq, (mmsize/2)*3, tmpq
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%else
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movaps m0, [inq + 0*mmsize]
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movaps m1, [inq + 1*mmsize]
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movaps m2, [inq + 2*mmsize]
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movaps m3, [inq + 3*mmsize]
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%endif
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FFT8 m0, m1, m2, m3, m4, m5
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@ -728,12 +736,22 @@ cglobal fft8_float, 4, 4, 6, ctx, out, in, tmp
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movups [outq + 3*mmsize], m1
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RET
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%endmacro
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FFT8_FN float, 1
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FFT8_FN ns_float, 0
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%macro FFT16_FN 2
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INIT_YMM avx
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cglobal fft8_float, 4, 4, 4, ctx, out, in, tmp
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cglobal fft8_ %+ %1, 4, 4, 4, ctx, out, in, tmp
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%if %2
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mov ctxq, [ctxq + AVTXContext.map]
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LOAD64_LUT m0, inq, ctxq, (mmsize/2)*0, tmpq, m2
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LOAD64_LUT m1, inq, ctxq, (mmsize/2)*1, tmpq, m3
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%else
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movaps m0, [inq + 0*mmsize]
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movaps m1, [inq + 1*mmsize]
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%endif
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FFT8_AVX m0, m1, m2, m3
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@ -747,16 +765,26 @@ cglobal fft8_float, 4, 4, 4, ctx, out, in, tmp
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vextractf128 [outq + 16*3], m0, 1
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RET
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%endmacro
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%macro FFT16_FN 1
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FFT16_FN float, 1
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FFT16_FN ns_float, 0
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%macro FFT16_FN 3
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INIT_YMM %1
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cglobal fft16_float, 4, 4, 8, ctx, out, in, tmp
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cglobal fft16_ %+ %2, 4, 4, 8, ctx, out, in, tmp
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%if %3
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movaps m0, [inq + 0*mmsize]
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movaps m1, [inq + 1*mmsize]
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movaps m2, [inq + 2*mmsize]
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movaps m3, [inq + 3*mmsize]
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%else
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mov ctxq, [ctxq + AVTXContext.map]
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LOAD64_LUT m0, inq, ctxq, (mmsize/2)*0, tmpq, m4
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LOAD64_LUT m1, inq, ctxq, (mmsize/2)*1, tmpq, m5
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LOAD64_LUT m2, inq, ctxq, (mmsize/2)*2, tmpq, m6
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LOAD64_LUT m3, inq, ctxq, (mmsize/2)*3, tmpq, m7
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%endif
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FFT16 m0, m1, m2, m3, m4, m5, m6, m7
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@ -777,25 +805,40 @@ cglobal fft16_float, 4, 4, 8, ctx, out, in, tmp
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RET
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%endmacro
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FFT16_FN avx
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FFT16_FN fma3
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FFT16_FN avx, float, 0
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FFT16_FN avx, ns_float, 1
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FFT16_FN fma3, float, 0
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FFT16_FN fma3, ns_float, 1
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%macro FFT32_FN 1
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%macro FFT32_FN 3
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INIT_YMM %1
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cglobal fft32_float, 4, 4, 16, ctx, out, in, tmp
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cglobal fft32_ %+ %2, 4, 4, 16, ctx, out, in, tmp
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%if %3
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movaps m4, [inq + 4*mmsize]
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movaps m5, [inq + 5*mmsize]
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movaps m6, [inq + 6*mmsize]
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movaps m7, [inq + 7*mmsize]
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%else
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mov ctxq, [ctxq + AVTXContext.map]
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LOAD64_LUT m4, inq, ctxq, (mmsize/2)*4, tmpq, m8, m9
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LOAD64_LUT m5, inq, ctxq, (mmsize/2)*5, tmpq, m10, m11
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LOAD64_LUT m6, inq, ctxq, (mmsize/2)*6, tmpq, m12, m13
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LOAD64_LUT m7, inq, ctxq, (mmsize/2)*7, tmpq, m14, m15
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%endif
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FFT8 m4, m5, m6, m7, m8, m9
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%if %3
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movaps m0, [inq + 0*mmsize]
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movaps m1, [inq + 1*mmsize]
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movaps m2, [inq + 2*mmsize]
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movaps m3, [inq + 3*mmsize]
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%else
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LOAD64_LUT m0, inq, ctxq, (mmsize/2)*0, tmpq, m8, m9
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LOAD64_LUT m1, inq, ctxq, (mmsize/2)*1, tmpq, m10, m11
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LOAD64_LUT m2, inq, ctxq, (mmsize/2)*2, tmpq, m12, m13
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LOAD64_LUT m3, inq, ctxq, (mmsize/2)*3, tmpq, m14, m15
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%endif
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movaps m8, [tab_32_float]
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vperm2f128 m9, m9, [tab_32_float + 4*8 - 4*7], 0x23
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@ -836,8 +879,10 @@ cglobal fft32_float, 4, 4, 16, ctx, out, in, tmp
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%endmacro
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%if ARCH_X86_64
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FFT32_FN avx
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FFT32_FN fma3
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FFT32_FN avx, float, 0
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FFT32_FN avx, ns_float, 1
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FFT32_FN fma3, float, 0
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FFT32_FN fma3, ns_float, 1
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%endif
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%macro FFT_SPLIT_RADIX_DEF 1-2
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@ -878,9 +923,9 @@ ALIGN 16
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%endif
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%endmacro
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%macro FFT_SPLIT_RADIX_FN 1
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%macro FFT_SPLIT_RADIX_FN 3
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INIT_YMM %1
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cglobal fft_sr_float, 4, 8, 16, 272, lut, out, in, len, tmp, itab, rtab, tgt
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cglobal fft_sr_ %+ %2, 4, 8, 16, 272, lut, out, in, len, tmp, itab, rtab, tgt
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movsxd lenq, dword [lutq + AVTXContext.len]
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mov lutq, [lutq + AVTXContext.map]
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mov tgtq, lenq
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@ -888,17 +933,31 @@ cglobal fft_sr_float, 4, 8, 16, 272, lut, out, in, len, tmp, itab, rtab, tgt
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; Bottom-most/32-point transform ===============================================
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ALIGN 16
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.32pt:
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%if %3
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movaps m4, [inq + 4*mmsize]
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movaps m5, [inq + 5*mmsize]
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movaps m6, [inq + 6*mmsize]
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movaps m7, [inq + 7*mmsize]
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%else
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LOAD64_LUT m4, inq, lutq, (mmsize/2)*4, tmpq, m8, m9
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LOAD64_LUT m5, inq, lutq, (mmsize/2)*5, tmpq, m10, m11
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LOAD64_LUT m6, inq, lutq, (mmsize/2)*6, tmpq, m12, m13
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LOAD64_LUT m7, inq, lutq, (mmsize/2)*7, tmpq, m14, m15
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%endif
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FFT8 m4, m5, m6, m7, m8, m9
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%if %3
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movaps m0, [inq + 0*mmsize]
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movaps m1, [inq + 1*mmsize]
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movaps m2, [inq + 2*mmsize]
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movaps m3, [inq + 3*mmsize]
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%else
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LOAD64_LUT m0, inq, lutq, (mmsize/2)*0, tmpq, m8, m9
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LOAD64_LUT m1, inq, lutq, (mmsize/2)*1, tmpq, m10, m11
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LOAD64_LUT m2, inq, lutq, (mmsize/2)*2, tmpq, m12, m13
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LOAD64_LUT m3, inq, lutq, (mmsize/2)*3, tmpq, m14, m15
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%endif
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movaps m8, [tab_32_float]
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vperm2f128 m9, m9, [tab_32_float + 32 - 4*7], 0x23
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@ -913,7 +972,11 @@ ALIGN 16
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movaps [outq + 5*mmsize], m5
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movaps [outq + 7*mmsize], m7
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%if %3
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add inq, 8*mmsize
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%else
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add lutq, (mmsize/2)*8
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%endif
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cmp lenq, 32
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jg .64pt
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@ -944,24 +1007,42 @@ ALIGN 16
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SWAP m4, m1
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SWAP m6, m3
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%if %3
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movaps tx1_e0, [inq + 0*mmsize]
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movaps tx1_e1, [inq + 1*mmsize]
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movaps tx1_o0, [inq + 2*mmsize]
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movaps tx1_o1, [inq + 3*mmsize]
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%else
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LOAD64_LUT tx1_e0, inq, lutq, (mmsize/2)*0, tmpq, tw_e, tw_o
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LOAD64_LUT tx1_e1, inq, lutq, (mmsize/2)*1, tmpq, tmp1, tmp2
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LOAD64_LUT tx1_o0, inq, lutq, (mmsize/2)*2, tmpq, tw_e, tw_o
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LOAD64_LUT tx1_o1, inq, lutq, (mmsize/2)*3, tmpq, tmp1, tmp2
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%endif
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FFT16 tx1_e0, tx1_e1, tx1_o0, tx1_o1, tw_e, tw_o, tx2_o0, tx2_o1
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%if %3
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movaps tx2_e0, [inq + 4*mmsize]
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movaps tx2_e1, [inq + 5*mmsize]
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movaps tx2_o0, [inq + 6*mmsize]
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movaps tx2_o1, [inq + 7*mmsize]
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%else
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LOAD64_LUT tx2_e0, inq, lutq, (mmsize/2)*4, tmpq, tmp1, tmp2
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LOAD64_LUT tx2_e1, inq, lutq, (mmsize/2)*5, tmpq, tw_e, tw_o
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LOAD64_LUT tx2_o0, inq, lutq, (mmsize/2)*6, tmpq, tmp1, tmp2
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LOAD64_LUT tx2_o1, inq, lutq, (mmsize/2)*7, tmpq, tw_e, tw_o
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%endif
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FFT16 tx2_e0, tx2_e1, tx2_o0, tx2_o1, tmp1, tmp2, tw_e, tw_o
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movaps tw_e, [tab_64_float]
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vperm2f128 tw_o, tw_o, [tab_64_float + 64 - 4*7], 0x23
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%if %3
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add inq, 8*mmsize
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%else
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add lutq, (mmsize/2)*8
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%endif
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cmp tgtq, 64
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je .deinterleave
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@ -1204,8 +1285,10 @@ FFT_SPLIT_RADIX_DEF 131072
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%endmacro
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%if ARCH_X86_64
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FFT_SPLIT_RADIX_FN avx
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FFT_SPLIT_RADIX_FN avx, float, 0
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FFT_SPLIT_RADIX_FN avx, ns_float, 1
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%if HAVE_AVX2_EXTERNAL
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FFT_SPLIT_RADIX_FN avx2
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FFT_SPLIT_RADIX_FN avx2, float, 0
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FFT_SPLIT_RADIX_FN avx2, ns_float, 1
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%endif
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%endif
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@ -23,6 +23,10 @@
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#include "config.h"
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/* These versions already do what we need them to do. */
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#define ff_tx_fft2_ns_float_sse3 ff_tx_fft2_float_sse3
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#define ff_tx_fft4_ns_float_sse2 ff_tx_fft4_fwd_float_sse2
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#define DECL_INIT_FN(basis, interleave) \
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static av_cold int \
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ff_tx_fft_sr_codelet_init_b ##basis## _i ##interleave## _x86 \
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@ -35,90 +39,102 @@ static av_cold int \
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{ \
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const int inv_lookup = opts ? opts->invert_lookup : 1; \
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ff_tx_init_tabs_float(len); \
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return ff_tx_gen_split_radix_parity_revtab(s, inv_lookup, \
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basis, interleave); \
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if (cd->max_len == 2) \
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return ff_tx_gen_ptwo_revtab(s, inv_lookup); \
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else \
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return ff_tx_gen_split_radix_parity_revtab(s, inv_lookup, \
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basis, interleave); \
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}
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#define ff_tx_fft_sr_codelet_init_b0_i0_x86 NULL
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DECL_INIT_FN(8, 0)
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DECL_INIT_FN(8, 2)
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#define DECL_SR_CD_DEF(fn_name, len, init_fn, fn_prio, cpu, fn_flags) \
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void ff_tx_ ##fn_name(AVTXContext *s, void *out, void *in, ptrdiff_t stride); \
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static const FFTXCodelet ff_tx_ ##fn_name## _def = { \
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.name = #fn_name, \
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.function = ff_tx_ ##fn_name, \
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.type = TX_TYPE(FFT), \
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.flags = FF_TX_OUT_OF_PLACE | FF_TX_ALIGNED | fn_flags, \
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.factors[0] = 2, \
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.min_len = len, \
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.max_len = len, \
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.init = ff_tx_fft_sr_codelet_init_ ##init_fn## _x86, \
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.cpu_flags = AV_CPU_FLAG_ ##cpu, \
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.prio = fn_prio, \
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#define DECL_CD_DEF(fn, t, min, max, f1, f2, i, p, c, f) \
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void ff_tx_ ##fn(AVTXContext *s, void *out, void *in, ptrdiff_t stride); \
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static const FFTXCodelet ff_tx_ ##fn## _def = { \
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.name = #fn, \
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.function = ff_tx_ ##fn, \
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.type = TX_TYPE(t), \
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.flags = FF_TX_ALIGNED | f, \
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.factors = { f1, f2 }, \
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.min_len = min, \
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.max_len = max, \
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.init = ff_tx_ ##i## _x86, \
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.cpu_flags = c, \
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.prio = p, \
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};
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#define DECL_SR_CD_DEF(fn_name, len, init_fn, fn_prio, cpu, fn_flags) \
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DECL_CD_DEF(fn_name, FFT, len, len, 2, 0, \
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fft_sr_codelet_init_ ##init_fn, fn_prio, \
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AV_CPU_FLAG_ ##cpu, fn_flags) \
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DECL_SR_CD_DEF(fft2_float_sse3, 2, b0_i0, 128, SSE3, AV_TX_INPLACE)
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DECL_SR_CD_DEF(fft2_ns_float_sse3, 2, b8_i0, 192, SSE3, AV_TX_INPLACE | FF_TX_PRESHUFFLE)
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DECL_SR_CD_DEF(fft4_fwd_float_sse2, 4, b0_i0, 128, SSE2, AV_TX_INPLACE | FF_TX_FORWARD_ONLY)
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DECL_SR_CD_DEF(fft4_inv_float_sse2, 4, b0_i0, 128, SSE2, AV_TX_INPLACE | FF_TX_INVERSE_ONLY)
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DECL_SR_CD_DEF(fft4_ns_float_sse2, 4, b8_i0, 192, SSE2, AV_TX_INPLACE | FF_TX_PRESHUFFLE)
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DECL_SR_CD_DEF(fft8_float_sse3, 8, b8_i0, 128, SSE3, AV_TX_INPLACE)
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DECL_SR_CD_DEF(fft8_ns_float_sse3, 8, b8_i0, 192, SSE3, AV_TX_INPLACE | FF_TX_PRESHUFFLE)
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DECL_SR_CD_DEF(fft8_float_avx, 8, b8_i0, 256, AVX, AV_TX_INPLACE)
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DECL_SR_CD_DEF(fft8_ns_float_avx, 8, b8_i0, 320, AVX, AV_TX_INPLACE | FF_TX_PRESHUFFLE)
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DECL_SR_CD_DEF(fft16_float_avx, 16, b8_i2, 256, AVX, AV_TX_INPLACE)
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DECL_SR_CD_DEF(fft16_ns_float_avx, 16, b8_i2, 320, AVX, AV_TX_INPLACE | FF_TX_PRESHUFFLE)
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DECL_SR_CD_DEF(fft16_float_fma3, 16, b8_i2, 288, FMA3, AV_TX_INPLACE)
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DECL_SR_CD_DEF(fft16_ns_float_fma3, 16, b8_i2, 352, FMA3, AV_TX_INPLACE | FF_TX_PRESHUFFLE)
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#if ARCH_X86_64
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DECL_SR_CD_DEF(fft32_float_avx, 32, b8_i2, 256, AVX, AV_TX_INPLACE)
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DECL_SR_CD_DEF(fft32_ns_float_avx, 32, b8_i2, 320, AVX, AV_TX_INPLACE | FF_TX_PRESHUFFLE)
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DECL_SR_CD_DEF(fft32_float_fma3, 32, b8_i2, 288, FMA3, AV_TX_INPLACE)
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DECL_SR_CD_DEF(fft32_ns_float_fma3, 32, b8_i2, 352, FMA3, AV_TX_INPLACE | FF_TX_PRESHUFFLE)
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void ff_tx_fft_sr_float_avx(AVTXContext *s, void *out, void *in, ptrdiff_t stride);
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const FFTXCodelet ff_tx_fft_sr_float_avx_def = {
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.name = "fft_sr_float_avx",
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.function = ff_tx_fft_sr_float_avx,
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.type = TX_TYPE(FFT),
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.flags = FF_TX_ALIGNED | FF_TX_OUT_OF_PLACE,
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.factors[0] = 2,
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.min_len = 64,
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.max_len = 131072,
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.init = ff_tx_fft_sr_codelet_init_b8_i2_x86,
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.cpu_flags = AV_CPU_FLAG_AVX,
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.prio = 256,
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};
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DECL_CD_DEF(fft_sr_float_avx, FFT, 64, 131072, 2, 0, fft_sr_codelet_init_b8_i2,
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256, AV_CPU_FLAG_AVX,
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FF_TX_OUT_OF_PLACE)
|
||||
|
||||
DECL_CD_DEF(fft_sr_ns_float_avx, FFT, 64, 131072, 2, 0, fft_sr_codelet_init_b8_i2,
|
||||
320, AV_CPU_FLAG_AVX,
|
||||
FF_TX_OUT_OF_PLACE | AV_TX_INPLACE | FF_TX_PRESHUFFLE)
|
||||
|
||||
#if HAVE_AVX2_EXTERNAL
|
||||
void ff_tx_fft_sr_float_avx2(AVTXContext *s, void *out, void *in, ptrdiff_t stride);
|
||||
const FFTXCodelet ff_tx_fft_sr_float_avx2_def = {
|
||||
.name = "fft_sr_float_avx2",
|
||||
.function = ff_tx_fft_sr_float_avx2,
|
||||
.type = TX_TYPE(FFT),
|
||||
.flags = FF_TX_ALIGNED | FF_TX_OUT_OF_PLACE,
|
||||
.factors[0] = 2,
|
||||
.min_len = 64,
|
||||
.max_len = 131072,
|
||||
.init = ff_tx_fft_sr_codelet_init_b8_i2_x86,
|
||||
.cpu_flags = AV_CPU_FLAG_AVX2,
|
||||
.prio = 288,
|
||||
};
|
||||
DECL_CD_DEF(fft_sr_float_avx2, FFT, 64, 131072, 2, 0, fft_sr_codelet_init_b8_i2,
|
||||
288, AV_CPU_FLAG_AVX2,
|
||||
FF_TX_OUT_OF_PLACE)
|
||||
|
||||
DECL_CD_DEF(fft_sr_ns_float_avx2, FFT, 64, 131072, 2, 0, fft_sr_codelet_init_b8_i2,
|
||||
352, AV_CPU_FLAG_AVX2,
|
||||
FF_TX_OUT_OF_PLACE | AV_TX_INPLACE | FF_TX_PRESHUFFLE)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
const FFTXCodelet * const ff_tx_codelet_list_float_x86[] = {
|
||||
/* Split-Radix codelets */
|
||||
&ff_tx_fft2_float_sse3_def,
|
||||
&ff_tx_fft2_ns_float_sse3_def,
|
||||
&ff_tx_fft4_fwd_float_sse2_def,
|
||||
&ff_tx_fft4_inv_float_sse2_def,
|
||||
&ff_tx_fft4_ns_float_sse2_def,
|
||||
&ff_tx_fft8_float_sse3_def,
|
||||
&ff_tx_fft8_ns_float_sse3_def,
|
||||
&ff_tx_fft8_float_avx_def,
|
||||
&ff_tx_fft8_ns_float_avx_def,
|
||||
&ff_tx_fft16_float_avx_def,
|
||||
&ff_tx_fft16_ns_float_avx_def,
|
||||
&ff_tx_fft16_float_fma3_def,
|
||||
&ff_tx_fft16_ns_float_fma3_def,
|
||||
|
||||
#if ARCH_X86_64
|
||||
&ff_tx_fft32_float_avx_def,
|
||||
&ff_tx_fft32_ns_float_avx_def,
|
||||
&ff_tx_fft32_float_fma3_def,
|
||||
&ff_tx_fft32_ns_float_fma3_def,
|
||||
|
||||
/* Standalone transforms */
|
||||
&ff_tx_fft_sr_float_avx_def,
|
||||
&ff_tx_fft_sr_ns_float_avx_def,
|
||||
#if HAVE_AVX2_EXTERNAL
|
||||
&ff_tx_fft_sr_float_avx2_def,
|
||||
&ff_tx_fft_sr_ns_float_avx2_def,
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user